Maximizing Power Efficiency with Asymmetric Multicore Systems

Fedorova, Saez, Shelepov, Prieto

power efficiency optimization asymmetric multicore parallel architecture

@article{fedorova:communications2009,
  title={Maximizing Power Efficiency with Asymmetric Multicore Systems},
  author={Alexandra Fedorova and Juan Carlos Saez and
          Daniel Shelepov and Manuel Prieto}
  journal={Communications of the {ACM}},
  year={2009},
  month={December},
  volume={52},
  number={12}
}

Processors are being designed with asymmetric cores

• Some with faster serial processing but more power consumption
• Many smaller cores with slower processing, but more parallelism and lower power consumption

Scheduler can assign processes based on some profile to these cores

• Intense serial computation goes on faster processor
• Better parallelized or more memory intensive tasks put on slower cores

Needs to monitor processes to determine what sort of phase they are in: Serial or parallel

• Tradeoff costs in switching versus savings gained
• Several approaches, costs, difficulties in such profiling